The exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a flip-flop circuit, which is used to generate an output signal synchronized with an input clock signal, and a duty cycle ratio correction circuit, which is used to correct a duty cycle ratio of the input clock signal to 50:50 by using the flip-flop circuit. Throughout the following specification and in the drawing figures the terms “duty ratio” and “duty cycle ratio” are used interchanneably.
Generally, semiconductor devices, including double data rate synchronous DRAM (DDR SDRAM), are under development toward high capacity, high-speed operation, miniaturization, and low power consumption. In an effort to achieve the high-speed operation, a frequency of an external clock signal is increased, and a semiconductor memory device is designed to operate at high speed by generating an internal clock signal in synchronization with the external clock signal. However, there are limitations to increasing the frequency of the external clock signal. To overcome such limitations, methods for increasing the utilization of an external clock signal have been used, with one of them being a double data rate (DDR) scheme.
While a single data rate (SDR) scheme outputs one data, in synchronization with a rising edge of a clock signal, in one cycle of the clock signal, a DDR scheme outputs two data, in synchronization with rising and falling edges of a clock signal, in one cycle of the clock signal. Therefore, when the same external clock signal is input, the DDR scheme has double the data processing ability of the SDRAM scheme.
The DDR scheme seeks to ensure the duty ratio of the clock signal is 50:50 because it outputs the data at the rising and falling edges of the clock signal. If the duty ratio is not 50:50 due to jitter components of the clock signal or other factors, the data output timing becomes distorted and thus the semiconductor memory device cannot ensure a stable data output operation. Therefore, a duty ratio correction circuit is provided inside the semiconductor memory device.
FIG. 1 is a circuit diagram of a conventional duty ratio correction circuit.
Referring to FIG. 1, the duty ratio correction circuit includes a first weighting unit 110, a second weighting unit 130, and a clock output unit 150.
The first weighting unit 110 gives a weight to a rising clock signal RCLK, and includes a plurality of inverters respectively configured to be enabled in response to first to fourth weight control signals CTR0 and /CTR0, CTR1 and /CTR1, CTR2 and /CTR2, CTR3 and /CTR3.
The second weighting unit 130 gives a weight to a falling clock signal FCLK, an includes a plurality of inverters respectively configured to be enabled in response to first to fourth weight control signals CTR0 and /CTR0, CTR1 and /CTR1, CTR2 and /CTR2, CTR3 and /CTR3.
The clock output unit 150 receives an output signal generated at a common node SUM to output an internal clock signal CLK_INN.
An operation of the conventional duty ratio correction circuit will be described briefly.
First, the operation of the inverters included in the first weighting unit 110 is opposite to the operation of the inverters included in the second weighting unit 130. In other words, if three inverters of the first weighting unit 110 are enabled, one inverter of the second weighting unit 130 is enabled. If one inverter of the first weighting unit 110 is enabled, three inverters of the second weighting unit 130 are enabled.
The first weighting unit 110 gives a weight to the rising clock signal RCLK and outputs the weighted rising clock signal to the common node SUM, and the second weighting unit 130 gives a weight to the falling clock signal FCLK and outputs the weighted falling clock signal to the common node SUM. The weighted signals output from the first and second weighting units 110 and 130 collide with each other at the common node SUM to generate an internal clock signal CLK_INN with a corrected duty ratio.
As described above, the structure of the conventional duty ratio correction circuit corrects the duty ratio by using the plurality of inverters. The inverters occupy a relatively large area and consume a relatively large amount of current. This frustrates the development of the semiconductor memory device toward low power consumption and miniaturization. In addition, the conventional duty ratio correction circuit has problems due to process, voltage and temperature (PVT) variations, as discussed below.
FIG. 2 is a waveform diagram for explaining waveforms of the signals related to the duty ratio correction circuit of FIG. 1. The rising clock signal RCLK and the falling clock signal FCLK may be distorted according to the PVT variations, as shown by the waveforms of FIG. 2. As shown in FIG. 2, a logic high period of the rising clock signal RCLK may be much shorter than a logic high period of the falling clock signal FCLK.
Generally, a very accurate control is required when weighting the rising clock signal RCLK and the falling clock signal FCLK. If the weight control is inaccurate, a step waveform may be generated at the common node SUM as illustrated in FIG. 2. In this case, the duty ratio of the internal clock signal CLK_INN finally output from the duty ratio correction circuit is slightly corrected compared to the initial rising and falling clock signals RCLK and FCLK, but the duty ratio of 50:50 is not ensured.
Meanwhile, correction of the weight control is achieved by a mask revision after a wafer fab-out. However, the process of mask revision is expensive, and thus the production cost of the semiconductor memory device is raised.